FINALTERM EXAMINATION
Spring 2011
CS302- Digital Logic Design
Total 52 questions
40 MCQs
Question No: 1 ( M a r k s: 1 ) http://vuzs.net
A 8-bit serial in / parallel out shift
register contains the value “8”, _____ clock signal(s) will be required
to shift the value completely out of the register.
► 1
► 2
► 4
► 8
Question No: 2 ( M a r k s: 1 ) http://vuzs.net
In a sequential circuit the next state is determined by ________ and _______
► State variable, current state
► Current state, flip-flop output
► Current state and external input
► Input and clock signal applied
Question No: 3 ( M a r k s: 1 ) http://vuzs.net
The divide-by-60 counter in digital clock is implemented by using two cascading counters:
► Mod-6, Mod-10
► Mod-50, Mod-10
► Mod-10, Mod-50
► Mod-50, Mod-6
Question No: 4 ( M a r k s: 1 ) http://vuzs.net
In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained.
► True
► False
Question No: 5 ( M a r k s: 1 ) http://vuzs.net
The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop.
► Set-up time
► Hold time
► Pulse Interval time
► Pulse Stability time (PST)
Question No: 6 ( M a r k s: 1 ) http://vuzs.net
74HC163 has two enable input pins which are _______ and _________
► ENP, ENT
► ENI, ENC
► ENP, ENC
► ENT, ENI
Question No: 7 ( M a r k s: 1 ) http://vuzs.net
____________ is said to occur when multiple internal variables change due to change in one input variable
► Clock Skew
► Race condition
► Hold delay
► Hold and Wait
Question No: 8 ( M a r k s: 1 ) http://vuzs.net
The _____________ input overrides the ________ input
► Asynchronous, synchronous
► Synchronous, asynchronous
► Preset input (PRE), Clear input (CLR)
► Clear input (CLR), Preset input (PRE)
Question No: 9 ( M a r k s: 1 ) http://vuzs.net
A decade counter is __________.
► Mod-3 counter
► Mod-5 counter
► Mod-8 counter
► Mod-10 counter
Question No: 10 ( M a r k s: 1 ) http://vuzs.net
In asynchronous transmission when the transmission line is idle, _________
► It is set to logic low
► It is set to logic high
► Remains in previous state
► State of transmission line is not used to start transmission
Question No: 11 ( M a r k s: 1 ) http://vuzs.net
A Nibble consists of _____ bits
► 2
► 4
► 8
► 16
Question No: 12 ( M a r k s: 1 ) http://vuzs.net
The output of this circuit is always ________.
► 1
► 0
► A
►
Question No: 13 ( M a r k s: 1 ) http://vuzs.net
Excess-8 code assigns _______ to “-8”
► 1110
► 1100
► 1000
► 0000
Question No: 14 ( M a r k s: 1 ) http://vuzs.net
The voltage gain of the Inverting Amplifier is given by the relation ________
► Vout / Vin = - Rf / Ri
► Vout / Rf = - Vin / Ri
► Rf / Vin = - Ri / Vout
► Rf / Vin = Ri / Vout
Question No: 15 ( M a r k s: 1 ) http://vuzs.net
LUT is acronym for _________
► Look Up Table
► Local User Terminal
► Least Upper Time Period
► None of given options
Question No: 16 ( M a r k s: 1 ) http://vuzs.net
The three fundamental gates are ___________
► AND, NAND, XOR
► OR, AND, NAND
► NOT, NOR, XOR
► NOT, OR, AND
Question No: 17 ( M a r k s: 1 ) http://vuzs.net
The total amount of memory that is supported by any digital system depends upon ______
► The organization of memory
► The structure of memory
► The size of decoding unit
► The size of the address bus of the microprocessor
Question No: 18 ( M a r k s: 1 ) http://vuzs.net
Stack is an acronym for _________
► FIFO memory
► LIFO memory
► Flash Memory
► Bust Flash Memory
Question No: 19 ( M a r k s: 1 ) http://vuzs.net
Addition of two octal numbers “36” and “71” results in ________
► 213
► 123
► 127
► 345
Question No: 20 ( M a r k s: 1 ) http://vuzs.net
___________ is one of the examples of synchronous inputs.
► J-K input
► EN input
► Preset input (PRE)
► Clear Input (CLR)
Question No: 21 ( M a r k s: 1 ) http://vuzs.net
__________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.
► Race condition
► Clock Skew
► Ripple Effect
► None of given options
Question No: 22 ( M a r k s: 1 ) http://vuzs.net
Consider an up/down counter that
counts between 0 and 15, if external input(X) is “0” the counter counts
upward (0000 to 1111) and if external input (X) is “1” the counter
counts downward (1111 to 0000), now suppose that the present state is
“1100” and X=1, the next state of the counter will be ___________
► 0000
► 1101
► 1011
► 1111
Question No: 23 ( M a r k s: 1 ) http://vuzs.net
In a state diagram, the transition from a current state to the next state is determined by
► Current state and the inputs
► Current state and outputs
► Previous state and inputs
► Previous state and outputs
Question No: 24 ( M a r k s: 1 ) http://vuzs.net
________ is used to simplify the circuit that determines the next state.
► State diagram
► Next state table
► State reduction
► State assignment
Question No: 25 ( M a r k s: 1 ) http://vuzs.net
A 8-bit serial in / parallel out
shift register contains the value “8”, _____ clock signal(s) will be
required to shift the value completely out of the register.
► 1
► 2
► 4
► 8
Question No: 26 ( M a r k s: 1 ) http://vuzs.net
Assume that a 4-bit serial in/serial
out shift register is initially clear. We wish to store the nibble 1100.
What will be the 4-bit pattern after the second clock pulse?
(Right-most bit first.)
► 1100
► 0011
► 0000
► 1111
Question No: 27 ( M a r k s: 1 ) http://vuzs.net
LUT is acronym for _________
► Look Up Table
► Local User Terminal
► Least Upper Time Period
► None of given options
. Question No: 28 ( M a r k s: 1 ) http://vuzs.net
The diagram given below represents __________
► Demorgans law
► Associative law
► Product of sum form
► Sum of product form
Question No: 29 ( M a r k s: 1 ) http://vuzs.net
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________
► Doesn’t have an invalid state
► Sets to clear when both J = 0 and K = 0
► It does not show transition on change in pulse
► It does not accept asynchronous inputs
Question No: 30 ( M a r k s: 1 ) http://vuzs.net
A multiplexer with a register circuit converts _________
► Serial data to parallel
► Parallel data to serial
► Serial data to serial
► Parallel data to parallel
Question No: 31 ( M a r k s: 1 ) http://vuzs.net
A GAL is essentially a ________.
► Non-reprogrammable PAL
► PAL that is programmed only by the manufacturer
► Very large PAL
► Reprogrammable PAL
Question No: 32 ( M a r k s: 1 ) http://vuzs.net
in ____________, all the columns in the same row are either read or written.
► Sequential Access
► MOS Access
► FAST Mode Page Access
► None of given options
Question No: 33 ( M a r k s: 1 ) http://vuzs.net
In order to synchronize two devices that consume and produce data at different rates, we can use _________
► Read Only Memory
► Fist In First Out Memory
► Flash Memory
► Fast Page Access Mode Memory
Question No: 34 ( M a r k s: 1 ) http://vuzs.net
A positive edge-triggered flip-flop changes its state when ________________
► Low-to-high transition of clock
► High-to-low transition of clock
► Enable input (EN) is set
► Preset input (PRE) is set
Question No: ( M a r k s: 2 )
Write down at least two applications of a shiftregister.
Question No: ( M a r k s: 2 )
Explain memory expansion process.
Question No: ( M a r k s: 2 )
Draw the NOR based S-R Latch
Question No: ( M a r k s: 3 )
Explain Rotate Left Right Operation with the help of diagram.
Question No: ( M a r k s: 3 )
You are given the block diagram of 74HC190 integrated circuit up/down counter, explain the function of labeled inputs/outputs.
Question No: ( M a r k s: 5 )
Explain Memory Select or Enable Signals
Question No: ( M a r k s: 5 )
Explain the implementation of First In First Out (FIFO) Memory by using RAM.
Question No: ( M a r k s: 5 )
Explain application of demultiplexer
