Showing posts with label CS501. Show all posts

CS501 Current Assignment # 1 solution Fall 2012

| Sunday, 4 November 2012 | Leave a comment

Q1. Write an SRC assembly language program to evaluate the following expression:
f = 4(k+32) + 16(g-h)
 Note that your code should not change the source operands and also keep in mind that the SRC does not have a multiply instruction
Part b: 5 marks
Draw memory map table for the above program using the following scenario and assume that SRC uses 16-bit memory in this case.
.ORG  300      ; start the next line at address 300
k:         .DW                1          ;
g:         .DW                1          ;
h:         .DW                1          ;
f:          .DW                1          ;
;
.ORG 400       ; start the code at address 400
The code starts at address 400 and each instruction takes 16-bits in the memory.
Solution:

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CS501 Final term Subjective Paper 2010

| Sunday, 12 August 2012 | Leave a comment

CS501 - Advance Computer Architecture  
Final paper 8/11/10
http://vu-world.blogspot.com/
Q1) suppose an I/O system with a single disk gets (on average) 200 I/O request/second. Assume that average time for a disk to service an I/O request is 4ms. What is the utilization time? 3Marks
Q2) Give an example when DMA can be brought into use? 3Marks
Q3) convert the hexadecimal number B316 to base 10 5Marks
www.vuzs.net
Q4) Does DMA affects the relationship b/w the memory system and CPU system. Explain with example.
5Marks
Q5) consider a 128kb direct mapping with a line length of 32 bytes
  1. è Determine the number of bits in the address that refers to the bytes within the cache
  1. è
Q6) consider the following floating point’s numbers 3 marks
-0.5 X 10-3
Find out the sign, significant and exponent
Q7) why we represent sometime some numbers in sign magnitude form. 


CS501 Final term Subjective Solved Paper

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CS501-Advance Computer Architecture Final Term Solved Subjective Paper


What function is performed by the reset operation of a processor? What are the two types of reset operations?
Answer:
Reset operation is required to change the processor‘s state to a known, defined value. The two essential features of a reset instruction are clearing the control step counter and reloading the PC to a predefined value.
Hard ResetThe SRC performs a hard reset upon receiving a start (Strt) signal. This initializes the PC and the general registers.
Soft ResetThe SRC performs a soft reset upon receiving a reset (rst) signal. The soft reset results in initialization of PC only.
 What do you know about Hard disk? A hard disk drive (HDD; also hard drive, hard disk, or disk drive)[2] is a device for storing and retrieving digital information, primarily computer data. It consists of one or more rigid (hence "hard") rapidly rotating discs (often referred to as platters), coated with magnetic material and with magnetic heads arranged to write data to the surfaces and read it from them.
Hard drives are classified as non-volatile, random access, digital, magnetic, data storage devices. Introduced by IBM in 1956, hard disk drives have decreased in cost and physical size over the years while dramatically increasing in capacity and speed. Hard disk drives have been the dominant device for secondary storage of data in general purpose computers since the early 1960s.[3] They have maintained this position because advances in their recording capacity, cost, reliability, and speed have kept pace with the requirements for secondary storage.[3]
(0.23) 10 convert in base 2?
What is meant by Packet switching?Ans lecture no 34 ….(page no360)
Classification of fiber optics mode multimode and mono mode?Solution
 Multimode: this fiber has large diameter when light is injected, it is disperses, so the effective data rate is diereses.
Mono mode:its diameter is very small. So dispersion ios small and data rate is very high.
Considered a 64kb direct mapped catch with a line length of 32bytesa .determine the number of bits in the address that refer to the byte within a cache line.b.determine the number of bits in the address required  to select the cache line.Solution (lecture no 41 ) page 348 o
If a DRAM has 512 rows and its fresh time is 9ms .What shoul be the frequency of row refresh operation on the average?Solution
Refresh time =9ms
Number of rows =512
Therefore we have to do 512 rows refresh operation in 9ms interval.in other words one row refresh operation every( 9*10-³)/512=1.76*10  second
Structural RTL for not instruction not ra ,rbSolution in lecture no 13
Why we use matrix in decoder?

CS501 Final term Paper 2008

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FINALTERM EXAMINATION
Fall 2008
CS501- Advance Computer Architecture (Session - 1)

M a r k s: 75
CS501 Question No: 1
Which one of the following is the memory organization of SRC processor?
  • 28 * 8 bits
  • 216 * 8 bits
  • 232 * 8 bits
  • 264 * 8 bits
CS501 Question No: 2
Type A format of SRC uses -----------instructions
  • two
  • three
  • four
  • five
CS501 Question No: 3
The instruction ---------------will load
the register R3 with the contents of the memory
location M [PC+56]
  • Add R3, 56
  • lar R3, 56
  • ldr R3, 56
  • str R3, 56
CS501 Question No: 4
Which format of the instruction is called the accumulator?
  • 3-address instructions
  • 3-address instructions
  • 2-address instructions
  • 1-address instructions
  • 0-address instructions
CS501 Question No: 5
Which one of the following are the code size
and the Number of memory
bytes respectively for a 2-address instruction?
  • 4 bytes, 7 bytes
  • 7 bytes, 16 bytes
  • 10 bytes, 19 bytes
  • 13 bytes, 22 bytes
CS501 Question No: 6
Which operator is used to name registers, or part of registers, in the Register
Transfer Language?
  • :=
  • &
  • %
  • ©
CS501 Question No: 7
The transmission of data in which each character is self-contained units with its
own start and stop bits is -----------
  • Asynchronous
  • Synchronous
  • Parallel
  • All of the given options
CS501 Question No: 8
Circuitry that is used to move data is called -------------
  • Bus
  • Port
  • Disk
  • Memory
CS501 Question No: 9
Which one of the following is NOT a technique used when the CPU wants to
exchange data with a peripheral device?
  • Direct Memory Access (DMA).
  • Interrupt driven I/O
  • Programmed I/O
  • Virtual Memory
CS501 Question No: 10
Every time you press a key, an interrupt is generated.
This is an example of
  • Hardware interrupt
  • Software interrupt
  • Exception
  • All of the given
CS501 Question No: 11
The interrupts which are pre-programmed and the processor automatically finds
the address of the ISR using interrupt vector table are
  • Maskable
  • Non-maskable
  • Non-vectored
  • Vectored
CS501 Question No: 12
Which is the last instruction of the ISR that is to be executed when the ISR
terminates?
  • IRET
  • IRQ
  • INT
  • NMI
CS501 Question No: 13
If NMI and INTR both interrupts occur simultaneously, then which one has the
precedence over the other
 
  • NMI
  • INTR
  • IRET
  • All of the given
CS501 Question No: 14
Identify the following type of serial communication error condition:
The prior character that was received was not still read by the CPU and is
over written by a new received character.
  • Framing error
  • Parity error
  • Overrun error
  • Under-run error
CS501 Question No: 15
----------the device usually means reading its status register every so often until
the device's status changes to indicate that it has completed the request.
  • Executing
  • Interrupting
  • Masking
  • Polling
CS501 Question No: 16
Which I/O technique will be used by a sound card that may need to access data
stored in the computer's RAM?
  • Programmed I/O
  • Interrupt driven I/O
  • Direct memory access(DMA)
  • Polling
CS501 Question No: 17
For increased and better performance we use _____ which are usually made of glass.
  • Coaxial Cables
  • Twisted Pair Cables
  • Fiber Optic Cables
  • Shielded Twisted Pair Cables
CS501 Question No: 18
In _____ if we find some call party busy we can have provision of call waiting.
  • Delay System
  • Loss System
  • Single Server Model
  • None of the given
CS501 Question No: 19
In ____ technique memory is divided into segments of variable sizes depending upon
the requirements.
  • Paging
  • Segmentation
  • Fragmentation
  • None of the given
CS501 Question No: 20
For a request of data if the requested data is not present in the cache, it is called a _____
  • Cache Miss
  • Spatial Locality
  • Temporal Locality
  • Cache Hit
CS501 Question No: 21
An entire _____ memory can be erased in one or a few seconds which is much faster
than EPROM.
  • PROM
  • Cache
  • EEPROM
  • Flash Memory
CS501 Question No: 22
________chips have quartz windows and by applying ultraviolet light data can be
erased from them.
  • PROM
  • Flash Memory
  • EPROM
  • EEPROM
CS501 Question No: 23
The _______signal coming from the CPU tells the memory that some interaction is
required between the CPU and memory.
  • REQUEST
  • COMPLETE
None of the given
CS501 Question No: 24
______ is a combination of arithmetic, logic and shifter unit along with some
multiplexers and control unit.
  • Barrel Rotator
  • Control Unit
  • Flip Flop
  • ALU
CS501 Question No: 25
1. In Multiple Interrupt Line, a number of interrupt lines are provided between the
____________________ module.
  • CPU and the I/O
 
 
  • CPU and Memory
  • Memory and I/O
  • None of the given
CS501 Question No: 26
The data movement instructions ___________ data within the machine and to
or from input/output devices.
  • Store
  • Load
  • Move
  • None of given
CS501 Question No: 27
CRC has ------------ overhead as compared to Hamming code.
  • Equal
  • Greater
  • Lesser
  • None of the given
CS501 Question No: 28
The ________ is w-bit wide and contains a data word, directly connected to the data
bus which is b-bit wide memory address register (MAR) .
  • Instruction Register(IR)
  • memory address register (MAR)
  • memory Buffer Register(MBR)
  • Program counter (PC)
www.vuzs.net
CS501 Question No: 29
In_______technique, a particular block of data from main memory can be placed in
only one location into the cache memory .
  • Set Associative Mapping
  • Direct Mapping
  • Associative Mapping
  • Block Placement
CS501 Question No: 30
_______ indicate the availability of page in main memory.
  • Access Control Bits
  • Used Bits
  • Presence Bits
  • None of the given
CS501 Question No: 31 ( M a r k s: 1 )
What are the hardware interrupts in a computer system?Mention its utility.
CS501 Question No: 32 ( M a r k s: 1 )
Consider a LAN, using bus topology. If we replace the bus with a switch, what change
will occur in such a configuration?
CS501 Question No: 33 ( M a r k s: 2 )
Where do you find the utility of hardware interrupts in a computer system?
CS501 Question No: 34 ( M a r k s: 2 )
Differentiate between CPU register and Cache Memory.
CS501 Question No: 35 ( M a r k s: 3 )
Name three important schemes that are commonly used for error control.
CS501 Question No: 36 ( M a r k s: 3 )
What do you understand by the term data synchronization ?
Explain briefly the following schemes of data synchronization in your own words
Synchronous transmission
Asynchronous transmission
CS501 Question No: 37 ( M a r k s: 3 )
Differenciate between Spatial Locality And Temporal Locality .
CS501 Question No: 38 ( M a r k s: 5 )
Given a 16-bit parallel output port attached with the FALCON-A CPU as shown in the figure. The
port is mapped onto address DEh of the FALCON-A s I/O space. Sixteen LED branches are
used to display the data being received from the FALCON-A s data bus. Every LED branch is
wired in such a way that when a 1 appears on the particular data bus bit, it turns the LED on; a 0
turns it off.
Which LEDs will be ON when the instruction
out r2, 222
executes on the CPU? Assume r2 contains 1234h.
CS501 Question No: 39 ( M a r k s: 5 )
Consider a 4 way set-associative cache with 256KB capacity and 32 byte lines
a) How many sets are there in the cache?
b) How many bits of address are required to select a set in cache?
CS501 Question No: 40 ( M a r k s: 10 )
Describe the following features of FALCON-A Assembler
Symbol Table
I/O Ports
List File
Single Step
Error Log
CS501 Question No: 41 ( M a r k s: 10 )
How many platters are required for a 40GB disk if there are 1024
bytes/sector, 2048 sectors per track and 4096 tracks per platter
How many platters are required for a 80GB disk if there are 1024
bytes/sector, 2048 sectors per track and 4096 tracks per platter

CS501 Mid term Subjective Paper 2011

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CS501-Advance Computer Architecture-Current-Midterm-2011


Q1- What is Reset operation describe it types
Q2- Describe super scaler and VILW.
Q3- Write RTL functions and there was a rb +rc instruction
Q4- Write RTL functions and there was a rb +rc instruction
Q5-. Write the structural RTL for “ in ra, rb”
Write the Structural RTL description for un-conditional jump instruction for
uni-bus data path implementation. (5 Marks)

CS501 Mid term Paper 2011

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CS501 Advance Computer Architecture Midterm Paper 28-Nov-2011

1. What function is performed by the reset operation of a processor and differentiate Hard reset and Soft reset? [5 marks]
2. Write the Structural RTL for the mov instruction for uni-bus data path implementation. mov ra, rb       3 marks
3. Write the Structural RTL for shift right instruction. 2 marks
4. What is the use of "NOP" instruction in pipe lining? 3 marks               vuzs


Some MCQs are as follows

1). LPC: This control signal will enable write of the Program Counter, thus the new,
incremented value can be written into the PC if it is made available on the “in”
bus. Note that the ALSU is assumed to include an INC4 function.

2). Anything that interrupts the normal flow of execution of instructions in the
processor is called an exception.

3).What is the size of the memory space that is available to FALCON-A processor?

2^8 bytes
2^16 bytes
2^32 bytes
2^64 bytes

4). What is the working of Processor Status Word (PSW)?
To hold the current status of the processor.
To hold the address of the current process
To hold the instruction that the computer is currently processing vuzs
To hold the address of the next instruction in memory that is to be executed
 www.vuzs.net
5). What is the instruction length of the FALCON-E processor?

8 bits
16 bits
32 bits
64 bits

6). Which one of the following portions of an instruction represents the operation to be performed?
Address
Instruction code
Opcode
Operand

7). Which instruction is used to store register to memory using relative address?
ld instruction
ldr instruction
lar instruction
str instruction
Helping topic: SRC instruction format.

8). Which type of instructions help in changing the flow of the program as and when required? vuzs.net
Arithmetic
Control
Data transfer
Floating point


9). A MCQ about Power PC

10). which one of the following is 0-address based machine.

11). There was a very long MCQ not remember now but the options are,
VCON
FCON
ACON
LCON
I already found all of them keywords on handouts but there is nothing like this.

CS501 Mid term Paper 2010

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MIDTERM  EXAMINATION
Spring 2010
CS501- Advance Computer Architecture (Session - 5)
Time: 60 min
M a r k s: 38

Question No: 1    ( M a r k s: 1 )    http://vuzs.net
What is the instruction length of the SRC processor?
   ► 8 bits
    ► 16 bits
     ► 32 bits
     ► 64 bits
Question No: 2    ( M a r k s: 1 )    http://vuzs.net
 Which one of the following is the memory organization of FALCON-E processor?
► 28 * 8 bits
   ► 216 * 8 bits
  ► 232 * 8 bits
  ► 264 * 8 bits
 Question No: 3    ( M a r k s: 1 )    http://vuzs.net
 “If P = 1, then load the contents of register R1 into register R2”.
This statement can be written in RTL as
  ► R1 ¬ R2
        ► P: R1 ¬ R2
       ► P: R2 ¬ R1
      ► P: R2 ¬ R1,   P: R1 ¬ R2
 Question No: 4    ( M a r k s: 1 )    http://vuzs.net
The instruction ---------------will load the register R3 with the contents of the memory location M [PC+56]
►Add R3, 56
►lar R3, 56
►ldr R3, 56
►str R3, 56
Question No: 5    ( M a r k s: 1 )    http://vuzs.net
----------are faster than cache memory
 ► Accumulator register
► CPU registers
 ► I/O devices
► ROM
Question No: 6    ( M a r k s: 1 )    http://vuzs.net
 P:  R3 ¬ R5
MAR ¬ IR
These two are instructions written using RTL .If these two operations is to occur simultaneously then which symbol will we use to separate them so that it becomes a correct statement with the condition that two operations occur simultaneously?
  ► Arrow    ¬           
   ► Colon    :                   
 ► Comma  ,      
 ► Parentheses ()    
Question No: 7    ( M a r k s: 1 )    http://vuzs.net
 Prefetching can be considered a primitive form of-------------
►Pipelining 
 ►Multi-processing
►Self-execution
 ►Exception

   
Question No: 8    ( M a r k s: 1 )    http://vuzs.net
 The processor must have a way of saving information about its state or context so that it can be restored upon return from the -------------
►Exception
►Function
►Stack
►Thread
 Question No: 9    ( M a r k s: 1 )    http://vuzs.net
Which one of the following circuit design levels is called the gate level 
► Logic Design Level
► Circuit Level
► Mask Level
 ► None of the given
 Question No: 10    ( M a r k s: 1 )    http://vuzs.net
 __________ enable the input to the PC for receiving a value that is currently on the internal processor bus.
       ► LPC
       ► INC4
       ► LC
       ► Cout
 Question No: 11    ( M a r k s: 1 )    http://vuzs.net
________ operation is required to change the processor’s state to a known, defined value.
       ► Change
       ► Reset
       ► Update
       ► None of the given
 Question No: 12    ( M a r k s: 1 )    http://vuzs.net
 There are _________ types of reset operations in SRC
       ► Two
       ► Three
       ► Four
       ► Five
 Question No: 13    ( M a r k s: 1 )    http://vuzs.net
_____________ controller controls the sequence of the flow of micro instructions.
       ► Multiplexer
       ► Microprogram
       ► ALU
       ► None of the given
  Question No: 14    ( M a r k s: 1 )    http://vuzs.net
 FALCON-A processor bus has 16 lines or is 16-bits wide while that of SRC is __________ wide.
      ► 8-bits
       ► 24-bits
       ► 32-bits
       ► 64-bits
    Question No: 15    ( M a r k s: 1 )    http://vuzs.net
 Which of the following statement(s) is/are correct about Reduced Instruction Set Computer (RISC) architectures.
 (i)        The typical RISC machine instruction set is small, and is usually a subject of a CISC instruction set.
(ii)        No arithmetic or logical instruction can refer to the memory directly.
(iii)       A comparatively large number of user registers are available.
(iv)       Instructions can be easily decoded through hard-wired control units.
     ► (i) and (iii) only
       ► (i), (iii) and (iv)
       ► (i), (ii) and (iii) only
       ► (i),(ii),(iii) and (iv)
 Question No: 16    ( M a r k s: 1 )    http://vuzs.net
Which one of the following register holds the instruction that is being executed?
     ► Accumulator
       ► Address Mask
       ► Instruction Register
       ► Program Counter
   Question No: 17    ( M a r k s: 2 )
 Write the following statement of an Arithmetic Instruction  using RTL.
If op-code is 0, the instruction is ‘add’. The values in register rb and rc are added and the result is stored in register rc
Question No: 18    ( M a r k s: 2 )
Given below are the various fields of an SRC instruction register.
a)    operation code field :  op<4..0>
b)    target register field : ra<4..0>
c)    operand, address index, or branch target register : rb<4..0>
d)    second operand, conditional test, or shift count register: rc<4..0>
Rewrite these various fields of an SRC instruction, using the RTL.
 Question No: 19    ( M a r k s: 2 )
How can you define microprograQuestion No: 20    ( M a r k s: 3 )
What is the role of timing step generator in a processor?

 Question No: 21    ( M a r k s: 3 )
What is the utility of reset operation and when it is required?
 Question No: 22    ( M a r k s: 5 )
Write the Structural RTL description for un-conditional jump instruction for uni-bus data path implementation.

         jump [ra+c2]
Question No: 23    ( M a r k s: 5 )
 What function is performed by the reset operation of a processor? What are the two types of reset operations?
2nd paper
There were 23 questions 1-14 are mcqs others are questions
Q : DEFINE HARD RESET AND SOFT RESET OPERATIONS IN SRC
Q : Write two pipelining problem and define them briefly.
Q : What information is provided by the addressing modes of some processors?
Q : ELABORATE PRE-FATCHING CONCEPT?
Q : Write RTL functions and there was a rb +rc instruction.
Q : how we speed-up a computer?
Q : Write execution time of an instruction(there was a description too)
Q : Types of instructions
Q : How you represent register data field?

CS501 Mid term Solved Paper 2006

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CS501_MID_2006_PAPER 
CS501-Advance Computer Architecture
Midterm Special 2006
_____________all memory systems are dumb, in that they respond to only two
commands: read or write
Virtually
Logically
Physically
None of These
Q 2
Consider two programs having three types of instructions given as follows:
[10]
Number of
Data transfer instructions
Control instructions
ALSU instructions
Program 1
736
Program 2
12
53
Instructions Type
Control
ALSU
Data Transfer
CPI
534
Compare both the programs for the following parameters:
1. Instruction count ( IC )
2. Speed of execution ( ET )
Q 3
To access an operand in memory, the CPU must first generate an address, which it then
issues to the __________
MEMORY
REGISTER
DATA BUS
ALL OF ABOVE
Q 4
___________ or Branch instructions affect the order in which instructions are performed,
or control the flow of the program
Control
DATA MOVMENT
Arithmetic
LOGICAL
Q5
Reverse assemble the following SRC machine language instructions:
[10]
68C2003A h
Q6
An instruction that specifies one operand in memory and one operand in a register would
be known as a __________ address instruction.
2-1/2
1-1/2
02
Q7
The data movement instructions ___________ data within the machine and to or from
input/output devices
Store
LOAD
MOVE
NONE OF ABOVE.
Q8
Write short answers to the following questions: [3 x 5]
a. What is the advantage of a linker in the development of assembly language
programs?
Solution:-
The linker:
When developing large programs, different people working at the same time can
develop separate modules of functionality. These modules can then be ‘linked’ to
form a single module that can be loaded and executed. The modularity of
programs, that the linking step in assembly language makes possible, provides the
same convenience as it does in higher-level languages; namely abstraction and
separation of concerns. Once the functionality of a module has been verified for
correctness, it can be re-used in any number of other modules. The programmer
can focus on other parts of the program. This is the so-called “modular” approach,
or the “top-down” approach.
b. Define term “Single stepping”.
Solution:-
Single stepping:
Single stepping and breakpoints that allow the examination of the status of
the program and registers at desired points during execution.
c. Define term “Type checking”.
Solution:-

Type Checking:-
High-level languages provide various primitive data types, such as integer,
Boolean and a string, that a programmer can use. Type checking provides for the
verification of proper usage of these data types. It allows the compiler to determine
memory requirements for variables and helping in the detection of bad programming
practices.
On the other hand, there is generally no provision for type checking at the machine
level, and hence, no provision for type checking in assembly language. The machine only
sees strings of bits. Instructions interpret the strings as a type, and it is usually limited to
signed or unsigned integers and floating point numbers. A given 32-bit word might be an
instruction, an integer, a floating-point number, or 4 ASCII characters. It is the task of the
compiler writer to determine how high-level language data types will be implemented
using the data types available at the machine level, and how type checking will be
implemented.
d. Define term “Instruction set”.
Solution:-
Instruction Set
A collection of all possible machine language commands that a computer can understand
and execute is called its instruction set. Every processor has its own unique instruction
set. Therefore, programs written for one processor will generally not run on another
processor. This is quite unlike programs written in higher-level languages, which may be
portable. Assembly/machine languages are generally unique to the processors on which
they are run, because of the differences in computer architecture.
Three ways to list instructions in an instruction set of a computer:
• by function categories
• by an alphabetic ordering of mnemonics
• by an ascending order of op-codes
e. Why computer logic design is different from classical logic design?
Solution:-
Classical logic design versus computer logic design:
The traditional sequential circuit design techniques for a finite state machine are not
very practical when it comes to the design of a computer, in spite of the fact that a
computer is a finite state machine. The reason is that employing these techniques is
much too complex as the computer can assume hundreds of states.

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