MIDTERM EXAMINATION
Spring 2010
CS501- Advance Computer Architecture (Session - 5)
Time: 60 min
M a r k s: 38
Question No: 1 ( M a r k s: 1 ) http://vuzs.net
What is the instruction length of the SRC processor?
► 8 bits
► 16 bits
► 32 bits
► 64 bits
Question No: 2 ( M a r k s: 1 ) http://vuzs.net
Which one of the following is the memory organization of FALCON-E processor?
► 28 * 8 bits
► 216 * 8 bits
► 232 * 8 bits
► 264 * 8 bits
Question No: 3 ( M a r k s: 1 ) http://vuzs.net
“If P = 1, then load the contents of register R1 into register R2”.
This statement can be written in RTL as
► R1 ¬ R2
► P: R1 ¬ R2
► P: R2 ¬ R1
► P: R2 ¬ R1, P: R1 ¬ R2
Question No: 4 ( M a r k s: 1 ) http://vuzs.net
The instruction ---------------will load the register R3 with the contents of the memory location M [PC+56]
►Add R3, 56
►lar R3, 56
►ldr R3, 56
►str R3, 56
Question No: 5 ( M a r k s: 1 ) http://vuzs.net
----------are faster than cache memory
► Accumulator register
► CPU registers
► I/O devices
► ROM
Question No: 6 ( M a r k s: 1 ) http://vuzs.net
P: R3 ¬ R5
MAR ¬ IR
These
two are instructions written using RTL .If these two operations is to
occur simultaneously then which symbol will we use to separate them so
that it becomes a correct statement with the condition that two
operations occur simultaneously?
► Arrow ¬
► Colon :
► Comma ,
► Parentheses ()
Question No: 7 ( M a r k s: 1 ) http://vuzs.net
Prefetching can be considered a primitive form of-------------
►Pipelining
►Multi-processing
►Self-execution
►Exception
Question No: 8 ( M a r k s: 1 ) http://vuzs.net
The
processor must have a way of saving information about its state or
context so that it can be restored upon return from the -------------
►Exception
►Function
►Stack
►Thread
Question No: 9 ( M a r k s: 1 ) http://vuzs.net
Which one of the following circuit design levels is called the gate level
► Logic Design Level
► Circuit Level
► Mask Level
► None of the given
Question No: 10 ( M a r k s: 1 ) http://vuzs.net
__________ enable the input to the PC for receiving a value that is currently on the internal processor bus.
► LPC
► INC4
► LC
► Cout
Question No: 11 ( M a r k s: 1 ) http://vuzs.net
________ operation is required to change the processor’s state to a known, defined value.
► Change
► Reset
► Update
► None of the given
Question No: 12 ( M a r k s: 1 ) http://vuzs.net
There are _________ types of reset operations in SRC
► Two
► Three
► Four
► Five
Question No: 13 ( M a r k s: 1 ) http://vuzs.net
_____________ controller controls the sequence of the flow of micro instructions.
► Multiplexer
► Microprogram
► ALU
► None of the given
Question No: 14 ( M a r k s: 1 ) http://vuzs.net
FALCON-A processor bus has 16 lines or is 16-bits wide while that of SRC is __________ wide.
► 8-bits
► 24-bits
► 32-bits
► 64-bits
Question No: 15 ( M a r k s: 1 ) http://vuzs.net
Which of the following statement(s) is/are correct about Reduced Instruction Set Computer (RISC) architectures.
(i) The typical RISC machine instruction set is small, and is usually a subject of a CISC instruction set.
(ii) No arithmetic or logical instruction can refer to the memory directly.
(iii) A comparatively large number of user registers are available.
(iv) Instructions can be easily decoded through hard-wired control units.
► (i) and (iii) only
► (i), (iii) and (iv)
► (i), (ii) and (iii) only
► (i),(ii),(iii) and (iv)
Question No: 16 ( M a r k s: 1 ) http://vuzs.net
Which one of the following register holds the instruction that is being executed?
► Accumulator
► Address Mask
► Instruction Register
► Program Counter
Question No: 17 ( M a r k s: 2 )
Write the following statement of an Arithmetic Instruction using RTL.
If op-code is 0, the instruction is ‘add’. The values in register rb and rc are added and the result is stored in register rc
Question No: 18 ( M a r k s: 2 )
Given below are the various fields of an SRC instruction register.
a) operation code field : op<4..0>
b) target register field : ra<4..0>
c) operand, address index, or branch target register : rb<4..0>
d) second operand, conditional test, or shift count register: rc<4..0>
Rewrite these various fields of an SRC instruction, using the RTL.
Question No: 19 ( M a r k s: 2 )
How can you define microprograQuestion No: 20 ( M a r k s: 3 )
What is the role of timing step generator in a processor?
Question No: 21 ( M a r k s: 3 )
What is the utility of reset operation and when it is required?
Question No: 22 ( M a r k s: 5 )
Write the Structural RTL description for un-conditional jump instruction for uni-bus data path implementation.
jump [ra+c2]
Question No: 23 ( M a r k s: 5 )
What function is performed by the reset operation of a processor? What are the two types of reset operations?
2nd paper
There were 23 questions 1-14 are mcqs others are questions
Q : DEFINE HARD RESET AND SOFT RESET OPERATIONS IN SRC
Q : Write two pipelining problem and define them briefly.
Q : What information is provided by the addressing modes of some processors?
Q : ELABORATE PRE-FATCHING CONCEPT?
Q : Write RTL functions and there was a rb +rc instruction.
Q : how we speed-up a computer?
Q : Write execution time of an instruction(there was a description too)
Q : Types of instructions
Q : How you represent register data field?
Q : DEFINE HARD RESET AND SOFT RESET OPERATIONS IN SRC
Q : Write two pipelining problem and define them briefly.
Q : What information is provided by the addressing modes of some processors?
Q : ELABORATE PRE-FATCHING CONCEPT?
Q : Write RTL functions and there was a rb +rc instruction.
Q : how we speed-up a computer?
Q : Write execution time of an instruction(there was a description too)
Q : Types of instructions
Q : How you represent register data field?
