CS501 Final term Paper 2008

FINALTERM EXAMINATION
Fall 2008
CS501- Advance Computer Architecture (Session - 1)

M a r k s: 75
CS501 Question No: 1
Which one of the following is the memory organization of SRC processor?
  • 28 * 8 bits
  • 216 * 8 bits
  • 232 * 8 bits
  • 264 * 8 bits
CS501 Question No: 2
Type A format of SRC uses -----------instructions
  • two
  • three
  • four
  • five
CS501 Question No: 3
The instruction ---------------will load
the register R3 with the contents of the memory
location M [PC+56]
  • Add R3, 56
  • lar R3, 56
  • ldr R3, 56
  • str R3, 56
CS501 Question No: 4
Which format of the instruction is called the accumulator?
  • 3-address instructions
  • 3-address instructions
  • 2-address instructions
  • 1-address instructions
  • 0-address instructions
CS501 Question No: 5
Which one of the following are the code size
and the Number of memory
bytes respectively for a 2-address instruction?
  • 4 bytes, 7 bytes
  • 7 bytes, 16 bytes
  • 10 bytes, 19 bytes
  • 13 bytes, 22 bytes
CS501 Question No: 6
Which operator is used to name registers, or part of registers, in the Register
Transfer Language?
  • :=
  • &
  • %
  • ©
CS501 Question No: 7
The transmission of data in which each character is self-contained units with its
own start and stop bits is -----------
  • Asynchronous
  • Synchronous
  • Parallel
  • All of the given options
CS501 Question No: 8
Circuitry that is used to move data is called -------------
  • Bus
  • Port
  • Disk
  • Memory
CS501 Question No: 9
Which one of the following is NOT a technique used when the CPU wants to
exchange data with a peripheral device?
  • Direct Memory Access (DMA).
  • Interrupt driven I/O
  • Programmed I/O
  • Virtual Memory
CS501 Question No: 10
Every time you press a key, an interrupt is generated.
This is an example of
  • Hardware interrupt
  • Software interrupt
  • Exception
  • All of the given
CS501 Question No: 11
The interrupts which are pre-programmed and the processor automatically finds
the address of the ISR using interrupt vector table are
  • Maskable
  • Non-maskable
  • Non-vectored
  • Vectored
CS501 Question No: 12
Which is the last instruction of the ISR that is to be executed when the ISR
terminates?
  • IRET
  • IRQ
  • INT
  • NMI
CS501 Question No: 13
If NMI and INTR both interrupts occur simultaneously, then which one has the
precedence over the other
 
  • NMI
  • INTR
  • IRET
  • All of the given
CS501 Question No: 14
Identify the following type of serial communication error condition:
The prior character that was received was not still read by the CPU and is
over written by a new received character.
  • Framing error
  • Parity error
  • Overrun error
  • Under-run error
CS501 Question No: 15
----------the device usually means reading its status register every so often until
the device's status changes to indicate that it has completed the request.
  • Executing
  • Interrupting
  • Masking
  • Polling
CS501 Question No: 16
Which I/O technique will be used by a sound card that may need to access data
stored in the computer's RAM?
  • Programmed I/O
  • Interrupt driven I/O
  • Direct memory access(DMA)
  • Polling
CS501 Question No: 17
For increased and better performance we use _____ which are usually made of glass.
  • Coaxial Cables
  • Twisted Pair Cables
  • Fiber Optic Cables
  • Shielded Twisted Pair Cables
CS501 Question No: 18
In _____ if we find some call party busy we can have provision of call waiting.
  • Delay System
  • Loss System
  • Single Server Model
  • None of the given
CS501 Question No: 19
In ____ technique memory is divided into segments of variable sizes depending upon
the requirements.
  • Paging
  • Segmentation
  • Fragmentation
  • None of the given
CS501 Question No: 20
For a request of data if the requested data is not present in the cache, it is called a _____
  • Cache Miss
  • Spatial Locality
  • Temporal Locality
  • Cache Hit
CS501 Question No: 21
An entire _____ memory can be erased in one or a few seconds which is much faster
than EPROM.
  • PROM
  • Cache
  • EEPROM
  • Flash Memory
CS501 Question No: 22
________chips have quartz windows and by applying ultraviolet light data can be
erased from them.
  • PROM
  • Flash Memory
  • EPROM
  • EEPROM
CS501 Question No: 23
The _______signal coming from the CPU tells the memory that some interaction is
required between the CPU and memory.
  • REQUEST
  • COMPLETE
None of the given
CS501 Question No: 24
______ is a combination of arithmetic, logic and shifter unit along with some
multiplexers and control unit.
  • Barrel Rotator
  • Control Unit
  • Flip Flop
  • ALU
CS501 Question No: 25
1. In Multiple Interrupt Line, a number of interrupt lines are provided between the
____________________ module.
  • CPU and the I/O
 
 
  • CPU and Memory
  • Memory and I/O
  • None of the given
CS501 Question No: 26
The data movement instructions ___________ data within the machine and to
or from input/output devices.
  • Store
  • Load
  • Move
  • None of given
CS501 Question No: 27
CRC has ------------ overhead as compared to Hamming code.
  • Equal
  • Greater
  • Lesser
  • None of the given
CS501 Question No: 28
The ________ is w-bit wide and contains a data word, directly connected to the data
bus which is b-bit wide memory address register (MAR) .
  • Instruction Register(IR)
  • memory address register (MAR)
  • memory Buffer Register(MBR)
  • Program counter (PC)
www.vuzs.net
CS501 Question No: 29
In_______technique, a particular block of data from main memory can be placed in
only one location into the cache memory .
  • Set Associative Mapping
  • Direct Mapping
  • Associative Mapping
  • Block Placement
CS501 Question No: 30
_______ indicate the availability of page in main memory.
  • Access Control Bits
  • Used Bits
  • Presence Bits
  • None of the given
CS501 Question No: 31 ( M a r k s: 1 )
What are the hardware interrupts in a computer system?Mention its utility.
CS501 Question No: 32 ( M a r k s: 1 )
Consider a LAN, using bus topology. If we replace the bus with a switch, what change
will occur in such a configuration?
CS501 Question No: 33 ( M a r k s: 2 )
Where do you find the utility of hardware interrupts in a computer system?
CS501 Question No: 34 ( M a r k s: 2 )
Differentiate between CPU register and Cache Memory.
CS501 Question No: 35 ( M a r k s: 3 )
Name three important schemes that are commonly used for error control.
CS501 Question No: 36 ( M a r k s: 3 )
What do you understand by the term data synchronization ?
Explain briefly the following schemes of data synchronization in your own words
Synchronous transmission
Asynchronous transmission
CS501 Question No: 37 ( M a r k s: 3 )
Differenciate between Spatial Locality And Temporal Locality .
CS501 Question No: 38 ( M a r k s: 5 )
Given a 16-bit parallel output port attached with the FALCON-A CPU as shown in the figure. The
port is mapped onto address DEh of the FALCON-A s I/O space. Sixteen LED branches are
used to display the data being received from the FALCON-A s data bus. Every LED branch is
wired in such a way that when a 1 appears on the particular data bus bit, it turns the LED on; a 0
turns it off.
Which LEDs will be ON when the instruction
out r2, 222
executes on the CPU? Assume r2 contains 1234h.
CS501 Question No: 39 ( M a r k s: 5 )
Consider a 4 way set-associative cache with 256KB capacity and 32 byte lines
a) How many sets are there in the cache?
b) How many bits of address are required to select a set in cache?
CS501 Question No: 40 ( M a r k s: 10 )
Describe the following features of FALCON-A Assembler
Symbol Table
I/O Ports
List File
Single Step
Error Log
CS501 Question No: 41 ( M a r k s: 10 )
How many platters are required for a 40GB disk if there are 1024
bytes/sector, 2048 sectors per track and 4096 tracks per platter
How many platters are required for a 80GB disk if there are 1024
bytes/sector, 2048 sectors per track and 4096 tracks per platter

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